Northrop Grumman has filed a patent for a power supply system that includes a voltage-limit power regulator, an instantaneous overvoltage sensor, and an overvoltage latch-off timer system. The system is designed to detect and respond to overvoltage conditions, with the latch-off timer system disabling the power regulator if a persistent overvoltage fault is detected. GlobalData’s report on Northrop Grumman gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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Power supply system with overvoltage protection and fault detection
A recently filed patent (Publication Number: US20230307903A1) describes a power supply system with an overvoltage protection mechanism. The system includes a power regulator that operates in voltage-limit mode and generates an output voltage. An instantaneous overvoltage sensor is used to detect any overvoltage condition associated with the output voltage.
The key feature of this system is the overvoltage latch-off timer system. When an overvoltage condition is detected, the latch-off timer is initiated. Importantly, the latch-off timer is not affected by the amplitude of the output voltage. After the expiration of the latch-off timer, the system checks for a persistent overvoltage fault. If such a fault is detected, a fault signal is generated to disable the voltage-limit power regulator.
The overvoltage latch-off timer system consists of a latch-off timer circuit and a finite state machine (FSM) controller system. The latch-off timer circuit initiates the latch-off timer and includes a charging switch and a timing capacitor. The charging switch closes in response to a latch voltage generated by the FSM controller system. The timing capacitor charges through the closed charging switch, generating a timing voltage.
The FSM controller system is responsible for detecting the persistent overvoltage fault. It includes a timer latch that generates the latch voltage based on the logic transition of the overvoltage signal. The latch voltage is maintained to charge the timing capacitor. A threshold detector in the latch-off timer circuit compares the timing voltage with a threshold voltage, providing a timer signal to the FSM controller system when the timing voltage is approximately equal to the threshold voltage, indicating the expiration of the latch-off timer.
The FSM controller system also includes a fault detector that generates the fault signal in response to the timer signal and programmable conditions. These programmable conditions can be based on a predetermined time duration or a predetermined number of clock cycles.
Additionally, the system includes an overvoltage nuisance detector that detects a nuisance overvoltage condition. If the overvoltage condition is not detected after the expiration of the latch-off timer but before the expiration of a nuisance overvoltage timer, a reset signal is generated. This reset signal unlatches the latch voltage, opens the charging switch, and discharges the timing capacitor to decrease the timing voltage.
Overall, this power supply system with an overvoltage latch-off timer provides effective protection against persistent overvoltage faults and nuisance overvoltage conditions, ensuring the safe operation of the power regulator.
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GlobalData, the leading provider of industry intelligence, provided the underlying data, research, and analysis used to produce this article.
GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
