Sital Technology’s enhanced bit rate (EBR) 1553 intellectual property core for FPGA is now available.
EBR-1553 is a 10Mbps bit rate protocol, which utilised the robust Mil-Std-1553 protocol over RS-485 transceivers in a hub-based point-to-point connection. Using network topology of a star between BC and remote terminals enables high-speed and robust data transfer.
Sital’s EBR-1553 IP core is based on Sital’s proven 1553 IP cores, with DDC enhanced mini-ace compatible interface. Bus controller, remote terminals and bus monitor IP core configurations are available. The core can work with any FPGA, and requires only standard RS-485 transceiver, which supports 10Mbps.
Users of Sital’s EBR-1553 IP core can select the core configuration (BC, RT, MT), clock frequency, memory configuration and FPGA family. The back-end interface can be targeted to a local-bus, PCI bus or simple FIFO / registers read / write bus.
The IP Core is provided with software drivers which can be compiled for Windows, Linux, QNX, VxWorks along with high-level API. The API is fully compatible with DDC API, so that software developers already used to the DDC interface can easily transfer their existing applications to EBR.
An EBR-1553 tester is also available, utilising the exact same hardware of the commonly used MultiComBox, with an updated firmware.
The EBR-1553 IP core joins the Sital’s growing family of Mil-Std-1553, Arinc 429, CAN, WB-194 and other reliable serial bus communication IP cores and solutions.