Kratos Defense & Security Solutions has filed a patent for a method and system to process a digital bit stream. The method involves dividing the bit stream into data packets and performing carrier recovery error calculations on different portions of the packets using a phase locked loop (PLL) function. The patent also includes combining the processed portions based on phase stitching. GlobalData’s report on Kratos Defense & Security Solutions gives a 360-degree view of the company including its patenting strategy. Buy the report here.
According to GlobalData’s company profile on Kratos Defense & Security Solutions, drone jamming technology was a key innovation area identified from patents. Kratos Defense & Security Solutions's grant share as of June 2023 was 1%. Grant share is based on the ratio of number of grants to total number of patents.
The patent is filed for a method of processing a digital bit stream
A recently filed patent (Publication Number: US20230188142A1) describes a method for processing a digital bit stream, specifically a digitized communication signal. The method involves dividing the digital bit stream into multiple data packets and processing them using various processing blocks.
In the first processing block, a carrier recovery error calculation is performed on a portion of the data packets. This calculation includes applying a phase locked loop (PLL) function to decimated data and performing a carrier recovery operation. Simultaneously, in the second processing block, the same carrier recovery error calculation is performed on another portion of the data packets. The first and second portions are then combined based on phase stitching.
Additionally, the method includes a third processing block where a timing recovery error calculation is performed on the first portion of data packets, along with a timing recovery operation. Similarly, in the fourth processing block, the same timing recovery error calculation and operation are performed on the second portion of data packets. The outputs of the third and fourth processing blocks are combined into blocks of time-corrected symbols, with frame boundaries located using frame markers.
The patent also mentions the use of single instructions, multiple data (SIMD) techniques to achieve high throughput in the processing blocks. Furthermore, it describes the use of different types of PLL functions, such as second order, third order, reversible, and reversible iterative PLL.
Another embodiment of the method described in the patent involves processing a frame-based digitized communication signal. The process includes dividing the digital bit stream into data packets, performing timing recovery error calculations and operations on the data packets in the first and second processing blocks, and combining the outputs into blocks of time-corrected symbols. These blocks are then searched for frame markers, and a correlator process and frequency tracking process are executed to locate frame boundaries and track carrier frequency.
Overall, this patent presents a method for efficiently processing digital bit streams in communication signals, utilizing various processing blocks and PLL functions for carrier and timing recovery. The use of SIMD techniques and frame markers enhances the accuracy and efficiency of the processing.
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